1. Field of the Invention
The present invention generally relates to a method to manufacture the multi-level interconnects of semiconductor devices, and more particularly to form a dual damascene.
2. Description of the Prior Art
Recently, the size of a semiconductor device has greatly been reduced and its structure has been highly integrated. When semiconductor devices of integrated circuits (IC) become highly integrated, the surface of the chips may not be supplied with enough area to make the interconnects. The requirement of matching interconnects increases when the devices shrink, many designs of integrated circuits have to use the dual damascene method. Moreover, it also uses the three-dimensional structure of multi-level interconnects at present in the deep sub-micron region, and inter-metal dielectric (IMD) as the dielectric material which is used to separate from each of the interconnects. A conducting wire which connects between the upper and the lower metal layers is called the via plug with in the semiconductor industry. In general, if an opening forms in the dielectric layer exposure to devices of the substrate in interconnects, it is called a via hole.
There are two methods for conventional via and interconnect processes, one method is that via and interconnect finish by oneself, wherein the method is that the dielectric is first formed on the metal layer, and then the photoresist layer (PR) is defined on the dielectric, and use the etching process to make the via, and deposit conduction material in the via by means of deposition to finish the via process, then deposit and define metal layer, afterward deposit the dielectric layer whereon. Conventional process forming the metal interconnect is that make the via window and the interconnect by means of two lithography process. Thus, it is need cumbrous steps of deposit and pattern. And yet, it will result in interconnects to be difficult patterned due to the multi layer connect layout is more daedal in the sub-quarter micron.
Hence, damascene interconnect structure is developed at present. According to particular of the process, it will compartmentalize three types, such as the single type, the dual type and the self-aligned type. The damascene is that etch the trench of interconnects in the dielectric, and then fill the metal as interconnect. This method can introduce metal that is difficult etched into the semiconductor without etching in the interconnect process. Therefore, this invention is the best method of the interconnect process in the sub-quarter micron.
Conventional dual damascene include two patterns, one is the deep patterns, that is the via patterns; another is the shallow patterns or the line patterns, that is the trench patterns. Conventional via first process for forming a dual damascene is shown as FIG. 1A to FIG. 1C, first of all, a first dielectric layer 110, an etching stop layer 120 and a second dielectric layer 130 are formed on the substrate 100 in order. Then a first photoresist layer 140 is formed on the second dielectric layer 130, and the first photoresist layer 140 is defined and patterned as a deep pattern area. Next, performing an etching process of the deep patterns by means of the first photoresist layer 140 as a etched mask, and then punching through the second dielectric layer 130, etching stop layer 120 and the first dielectric layer 110, while a via hole 150 is formed. After removing the first photoresist layer 140, a second photoresist layer 160 is formed on the second dielectric layer 130, and it is defined to form a shallow pattern area and expose the partial surface of the via hole 150 and the second dielectric layer 130 so that the horizontal size of the shallow patterns is large more then one of the deep patterns. Afterward performing an etching process of the shallow patterns by means of the second photoresist layer 160 as an etched mask and the etching stop layer 120 as an etching terminal point, so as to remove exposed partial surface of the second dielectric layer 130 and form a trench 170 having large horizontal size. Subsequently, the second photoresist layer 160 is removed to form the opening of the damascene 150 and 170. Final, proceed a interconnect process, since the above processes are well known in the prior art, which are not the focus of the present invention, hence will not be described in greater details.
Likewise, conventional trench first process for forming a dual damascene is shown as FIG. 2A to FIG. 2C, first of all, a first dielectric layer 210, an etching stop layer 220 and a second dielectric layer 230 are formed on the substrate 200 in order. Then a first photoresist layer 240 is formed on the second dielectric layer 230, and then it is defined to form a shallow pattern area and expose the partial surface of the second dielectric layer 230. Next, performing an etching process of the shallow patterns by means of the first photoresist layer 240 as an etched mask and the etching stop layer 220 as an etching terminal point, so as to remove exposed partial surface of the second dielectric layer 230 and form a trench 270. After removing the first photoresist layer 240, a second photoresist layer 260 is formed on the second dielectric layer 230 and the first dielectric layer 210, and then it is defined to form a shallow pattern area and expose the partial surface of the first dielectric layer 210 so that the horizontal size of the shallow patterns is large more then one of the deep patterns. Afterward performing an etching process of the deep patterns by means of the second photoresist layer 260 as an etched mask to form a trench 270 having a smaller horizontal size. Subsequently, the second photoresist layer 260 is removed to form the opening of the damascene 250 and 270. Final, proceed a interconnect process, since the above processes are well known in the prior art, which are not the focus of the present invention, hence will not be described in greater details.
Likewise, conventional embedded hard mask process for forming a dual damascene is shown as FIG. 3A to FIG. 3D, first of all, a first dielectric 310 and an embedded hard mask layer 320 are formed on the substrate 300 in order. Then a first photoresist layer 330 is formed on the embedded hard mask layer 320, and then it is defined to form a first predetermined etched area and expose the partial surface of the embedded hard mask layer 320. Next, performing an etching process by the first photoresist layer 330 as an etched mask to etch the first predetermined etched region and remove exposed partial surface of the embedded hard mask layer 320, and then form an etched region 340 on the first dielectric layer 310. After removing the first photoresist layer 330, a second dielectric layer 350 is formed on the first dielectric layer 310, and it is filled into the etched region 340. Subsequently, a second photoresist layer 360 is formed on the second dielectric layer 350 and it is defined to form a second predetermined etched region, which has the etched region 340, so that a partial surface of the second dielectric layer 350 is exposed. Afterward performing an etching process of the deep patterns by means of the second photoresist layer 360 as an etched mask to etch the second predetermined etched region, and then etching through the second dielectric layer 350 and the first dielectric layer 310, so as to form a trench 370 and a via hole 380. The second photoresist layer 360 is then removed to form the opening of the damascene 370 and 380. Final, proceed a interconnect process, since the above processes are well known in the prior art, which are not the focus of the present invention, hence will not be described in greater details.
The skill of the dual damascene is a method for forming via and interconnects. In the conventional dual damascene skill of above, it is necessary that the etching stop layer or the embedded hard mask have to be formed between two dielectric layers to perform the etching process. Therefore, there is a large fabricated cost due to the complex step for forming a dual damascene with conventional process. Moreover, performance of device is affected because the addition of etching stop layer or the embedded hard mask makes dielectric constant (K) to raise. Further, there are interface or adherence issues during forming multi-layer with various materials.
Furthermore, in the via first process, it is necessary that the dielectric layer has enough thickness, so as to avoid damaging semiconductor substrate during over-etching process for forming the via hole, but if the thickness of the dielectric layer is raised, the dielectric constant will be increased, and that device dimension, in sub-micron process, is difficult to be decreased. Hence, a protected layer, such as organic polymer, has to be added on the dielectric before forming the trench. Nevertheless, the organic material is difficult to remove so that process is very hard. Likewise, in the trench first process, there are depth of focus (DOF) issue or critical dimension (CD) issue that is difficult to control. On the other hand, both the etching process of the via first process and the trench first process is performed on the different surface, so that the process window is difficult to control after etching.
Furthermore, in the embedded hard mask process as above, if the selectivity between the embedded hard mask and the dielectric layer is not enough, the thickness of the dielectric layer will be raised. Therefore, the dielectric constant will also be increased. Moreover, there is a difference in height due to a raise in the thickness of the embedded hard mask, which will result in some issues, such as chemical mechanical polish (CMP) or a cap-fill that is difficult to control.
In accordance with the above description, a new and improved method for forming the dual damascene is therefore necessary, so as to raise the yield and quality of the follow-up process.
In accordance with the present invention, a new method for forming dual damascene process is provided that substantially overcomes drawbacks of above mentioned problems arise from the conventional methods.
Accordingly, it is an object of the present invention to provide a new method for forming the dual damascene. In the present invention, the etching process has only one time for forming the trench and the via hole at the same time, and that on the same surface, so as to control the process window and avoid the issues, such as DOF or CD. Therefore, the method of the present invention is effective in raising quality of the process.
Another object of the present invention is to provide a new method for patterning the dual damascene. In this invention, it is unnecessary to form the etched stop layer or embedded hard mask, so as to avoid increasing dielectric constant due to increased thickness of the dielectric layer or the addition of the etched stop layer. Accordingly, this invention can raise the performance of the logic circuit. Furthermore, the present invention can also prevent issues of interface or adherence. Therefore, the present invention can simplify the step of process to reduce cost in fabrication. Hence, the method of the present invention is easily able to conform to economic effect.
Still another object of the present invention is that provide a new method for patterning the dual damascene. In this invention, a dense region as an etched barrier layer is formed in the dielectric layer by an ion implantation, so as to substitute for the embedded hard mask or the etched stop layer in the conventional process. Hence, the method of this invention is suitable for use in the sub micron.
In accordance with the present invention, a new method for forming the dual damascene is disclosed. In one embodiment of the present invention, first of all, a substrate is provided, and a first dielectric layer is formed, thereon. Then a first photoresist layer is formed and defined on the first dielectric layer. Next, a dense region as an etched barrier layer is formed in the first dielectric layer by an ion implantation with photoresist layer as a mask. A second dielectric layer is formed on the first dielectric layer after the first photoresist layer is removed. Afterward forming a second photoresist layer on the second dielectric layer and defining a predetermined trench region to expose a partial surface of the second dielectric layer, wherein the partial surface of the second dielectric layer comprises the dense region. Subsequently, an etching process is performed by means of the second photoresist layer as an etched mask to etch through the second dielectric layer and the first dielectric layer until the substrate surface is exposed for patterning the dual damascene. Finally, removing the second photoresist layer and performing a interconnect process, since the above processes are well known in the prior art, which are not the focus of the present invention, hence will not be described in greater details.